AM1808B

Low-power applications processor, BGA361, AM1808B, TI, -0.5 to 1.4V, ±20mA

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Price:: US $14.60~20.70 / piece [Get Latest Price]

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	US $14.60~20.70

PartNumber:: AM1808B

Brand:: Texas Instruments - TI | Pack: BGA | D/C: 11+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-01-13

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Part Number:AM1808B
US $14.60 - 20.70
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Product Summary

The AM1808B is a Low-power applications processor based on ARM926EJ-S. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The AM1808B is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The AM1808B core uses pipelining so that all parts of the processor and memory system can operate continuously.

Parametrics

AM1808B absolute maximum ratings: (1)supply voltage range: -0.5 to 1.4V; (2)input voltage range: -0.3 to CVDD+0.3V; (3)output voltage range: -0.5 to DVDD+0.3V; (4)clamp current: ±20mA; (5)operating junction temperature ragne, Tj: 0 to 90℃; (6)storage temperature range, Tstg: -55 to 150℃; (7)ESD stress voltage, VESD: 100V.

Features

AM1808B features: (1)375/456-MHz ARM926EJ-S RISC Core; (2)ARM9 Memory Architecture; (3)Programmable Real-Time Unit Subsystem; (4)Enhanced Direct-Memory-Access Controller 3 (EDMA3); (5)Two External Memory Interfaces; (6)Three Configurable 16550 type UART Modules; (7) Two Serial Peripheral Interfaces (SPI); (8) Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO); (9)Two Master/Slave Inter-Integrated Circuit; (10)USB 2.0 OTG Port With Integrated PHY; (11)One Multichannel Audio Serial Port; (12)10/100 Mb/s Ethernet MAC (EMAC); (13)Three 64-Bit General-Purpose Timers; (14)One 64-bit General-Purpose/Watchdog Timer; (15)TwoEnhanced Pulse Width Modulators; (16)Three 32-Bit Enhanced Capture Modules; (17) 32-Bit Load/Store RISC architecture; (18)4K Byte instruction RAM per core; (19)512 Bytes data RAM per core; (20)PRU Subsystem (PRUSS) can be disabled via software to save power; (21)Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores.